Recently, the evolution of embedded systems has shown a strong trend towards application-specific, single-chip solutions. As a result, application-specific instruction set processors (ASIP) are replacing off-the-shelf processors in such systems-on-chip (SoC). Along with the processor cores, heterogeneous memory architectures play an important role as part of the system. As such architectures are highly optimized for a particular application domain, processor core and memory subsystem design should not be apart, but should merge into an efficient design process.
One of the key factors for a successful design of application-specific instruction set processors (ASIP) is an efficient architecture exploration phase. The objective of the architecture exploration is to reduce the huge design space in order to find the best-suited architecture for a given application under a number of constraints, such as performance, power consumption, chip size, and flexibility. Although there are a number of analytical approaches, large parts of the design space exploration still have to be carried out by simulating alternative architecture implementations. It becomes obvious that the design methodology and simulation performance have a significant impact on the efficiency of the exploration process, hence, on the quality of the architecture implementation and the design time.
The EXPRESSION language is one of few architecture description languages that allow for processor/memory co-exploration. Besides the ability to model the processor core on a micro-architecture level, the memory subsystem can be described by choosing from predefined memory models for DRAM, SRAM, caches, etc., and describing the interconnectivity as a netlist. However, the EXPRESSION language only supports cycle-accurate memory modeling.
Poseidon Technologies offers a memory architecture exploration tool, MemBrain, which is based on an extensible architecture description language XADL. However, similar to EXPRESSION, only cycle-accurate modeling is supported.
Dinero-IV is a memory simulator written in the C programming language, which is capable of modeling, arbitrary deep cache hierarchies. The simulator takes a memory trace as input and generates memory profiling data. Similar approaches are Active-Memory (see e.g., A. R. Lebeck and D. A. Wood “Active Memory: A New Abstraction for Memory-System Simulation”); MemSpy (see e.g., M. Martonosi, A. Gupta, and T. E. Anderson, “Memspy: Analyzing Memory System Bottlenecks in Programs”), and Tycho (see e.g., M. D. Hill, “Aspects of Cache Memory and Instruction Buffer Performance”). However, all these simulators are decoupled from the processor design process, and do not allow the modeling of very heterogeneous memory architectures.